With more and more widespread use of semiconductor chips, an increasing number of factors can cause electrostatic damages to the semiconductor chips. In the existing design of a chip, an electrostatic discharge (ESD) protection structure is often applied in the chip to reduce damages to the chip.
The design and application of an existing ESD protection circuit often include: gate ground N-type field-effect-transistor (GGNMOS) protection circuits, shallow trench isolation structure diode (STI diode) protection circuits, gated diode protection circuits, laterally diffused MOS (LDMOS) protection circuits, bipolar junction transistor (BJT) protection circuits, etc.
FIG. 1 illustrates an existing ESD protection structure. As shown in FIG. 1, the ESD protection structure includes an STI diode. The STI diode includes a substrate 10, an N-type well area 11 formed in the substrate 10, an isolation structure 12 formed in the N-type well area 11, and an N-type region 13n and a P-type region 13p formed at both sides of the isolation structure 12. The P-type region 13p is grounded, and an electrostatic voltage is applied on the N-type region 13n. 
The P-type region 13p and the N-type region 13n form a PN junction. The electrostatic voltage is applied on the N-type region 13n, and the P-type region 13p is grounded. When the electrostatic voltage reversely breaks down the PN junction, electrostatic charges can be released from the N-type region 13n to the ground through the N-type well area 11 and the P-type region 13p. 
However, such ESD protection structure often has issues of low manufacturing yield and unstable performance. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.